Support

Setup and support resources for the a2-6502 adapter. This page is based on the project README and points to the official repositories, software, profile files, and schematics.

Initial setup overview

Profile import paths

Install the pre-built LogicAnalyzer profile (required)

This is a critical setup step. Without the pre-built profile, channel names and assignments will not match the adapter wiring and captures will be confusing to interpret.

  1. Download the pre-built profile from the adapter profile folder. The file to install is profiles.json.
  2. Close the LogicAnalyzer application completely before copying files so it does not overwrite profile changes on exit.
  3. Locate your LogicAnalyzer profile directory:
    • macOS / Linux: $HOME/Library/Application Support/LogicAnalyzer
    • Windows: %userprofile%/appdata/roaming/logicanalyzer
  4. Backup your existing profile file first (recommended):
    • Rename the current file to profiles.backup.json, or copy it to a safe location.
  5. Install the pre-built profile:
    • If you do not already use custom profiles, copy the downloaded profiles.json directly into the profile directory.
    • If you already have a populated profiles.json, merge the a2-6502 profile entries into your existing file instead of replacing it.
  6. Start LogicAnalyzer and open your multi-device setup (one analyzer as master, second as slave).
  7. Open the profiles menu and select the Apple II / a2-6502 profile you installed.
  8. Run a quick capture and verify channel labeling:
    • CPU channels (clock, control, address, data) appear with expected names.
    • J3 channels map to CH-33 through CH-48 as listed in the tables on this page.
  9. If labels are missing or incorrect:
    • Confirm the file is in the correct OS path.
    • Confirm JSON formatting is valid (especially after manual merge).
    • Restart LogicAnalyzer after any profile file edits.
    • Recreate the multi-device pair and re-apply the profile.

USB mode notes

Channel maps and signal assignments

The tables below are copied from the project README so signal lookups are available directly on this page.

CPU + analyzer channel assignments

J1-Analyzer1 Signal Pin J2-Analyzer2 Signal
CH-1RDY1CH-25A8
CH-2IRQ\2CH-26A9
CH-3NMI\3CH-27A10
CH-4R/W\4CH-28A11
CH-5PHASE05CH-29A12
CH-6RES\6CH-30A13
CH-7D07CH-31A14
CH-8D18CH-32A15
CH-9D29CH-33J3-1
CH-10D310CH-34J3-2
CH-11D411CH-35J3-3
CH-12D512CH-36J3-4
CH-13D621CH-37J3-5
CH-14D722CH-38J3-6
CH-15A123CH-39J3-7
CH-16A224CH-40J3-8
CH-17A325CH-41J3-9
CH-18A426CH-42J3-10
CH-19A527CH-43J3-11
CH-20A628CH-44J3-12
CH-21A729CH-45J3-13
CH-22A830CH-46J3-14
CH-23Phase132CH-47J3-15
CH-24SYNC32CH-48J3-16

J3 header pin assignments

PIN-1 PIN-3 PIN-5 PIN-7 PIN-9 PIN-11 PIN-13 PIN-15
CH-33 CH-35 CH-37 CH-39 CH-41 CH-43 CH-45 CH-47
CH-34 CH-36 CH-38 CH-40 CH-42 CH-44 CH-46 CH-48
PIN-2 PIN-4 PIN-6 PIN-8 PIN-10 PIN-12 PIN-14 PIN-16