Support
Setup and support resources for the a2-6502 adapter. This page is based on the project README and points to the official repositories, software, profile files, and schematics.
Official repository
Hardware source, README, setup details, profile files, and project history for the adapter.
github.com/eositis/a2-6502-analyzer →LogicAnalyzer 6.5 beta
Recommended software line for this adapter because it supports profile import and mapping workflow.
6.5 beta discussion and release info →Adapter profile files
Import-ready profile set for channel assignments when using the a2-6502 deployment.
Gusmans-LogicAnalyzer profile folder →Production schematic (v1.5)
Board-level schematic PDF for electrical reference and debugging.
Open schematic PDF →Initial setup overview
- Install firmware on both LogicAnalyzer boards, then mount both analyzers onto the adapter.
- Link the two analyzer boards with three DuPont jumpers (top-to-top, middle-to-middle, bottom-to-bottom).
- Move the system CPU to the adapter socket (or use a spare CPU), keeping notch orientation correct.
- Insert the adapter into the host CPU socket and ensure full seating.
- Start LogicAnalyzer software, create a MultiDevice pair, set master/slave, then run a validation capture.
- If channel behavior looks wrong after pairing, recreate the device and swap which board is master.
Profile import paths
- macOS / Linux: copy
profiles.jsonto$HOME/Library/Application Support/LogicAnalyzer. - Windows: copy
profiles.jsonto%userprofile%/appdata/roaming/logicanalyzer. - If you already use a custom profile file, merge the adapter profile entries into your existing file.
Install the pre-built LogicAnalyzer profile (required)
This is a critical setup step. Without the pre-built profile, channel names and assignments will not match the adapter wiring and captures will be confusing to interpret.
-
Download the pre-built profile from
the adapter profile folder.
The file to install is
profiles.json. - Close the LogicAnalyzer application completely before copying files so it does not overwrite profile changes on exit.
-
Locate your LogicAnalyzer profile directory:
- macOS / Linux:
$HOME/Library/Application Support/LogicAnalyzer - Windows:
%userprofile%/appdata/roaming/logicanalyzer
- macOS / Linux:
-
Backup your existing profile file first (recommended):
- Rename the current file to
profiles.backup.json, or copy it to a safe location.
- Rename the current file to
-
Install the pre-built profile:
-
If you do not already use custom profiles, copy the downloaded
profiles.jsondirectly into the profile directory. -
If you already have a populated
profiles.json, merge the a2-6502 profile entries into your existing file instead of replacing it.
-
If you do not already use custom profiles, copy the downloaded
- Start LogicAnalyzer and open your multi-device setup (one analyzer as master, second as slave).
- Open the profiles menu and select the Apple II / a2-6502 profile you installed.
-
Run a quick capture and verify channel labeling:
- CPU channels (clock, control, address, data) appear with expected names.
- J3 channels map to CH-33 through CH-48 as listed in the tables on this page.
-
If labels are missing or incorrect:
- Confirm the file is in the correct OS path.
- Confirm JSON formatting is valid (especially after manual merge).
- Restart LogicAnalyzer after any profile file edits.
- Recreate the multi-device pair and re-apply the profile.
USB mode notes
- Use two USB cables, one per analyzer board.
- Set the adapter jumper/switch to USB mode for normal tethered use.
- Reference voltage is typically
EXT(Apple II 5V rail reference). - Wi-Fi mode should only be used when the analyzers are configured for full wireless operation.
Channel maps and signal assignments
The tables below are copied from the project README so signal lookups are available directly on this page.
CPU + analyzer channel assignments
| J1-Analyzer1 | Signal | Pin | J2-Analyzer2 | Signal |
|---|---|---|---|---|
| CH-1 | RDY | 1 | CH-25 | A8 |
| CH-2 | IRQ\ | 2 | CH-26 | A9 |
| CH-3 | NMI\ | 3 | CH-27 | A10 |
| CH-4 | R/W\ | 4 | CH-28 | A11 |
| CH-5 | PHASE0 | 5 | CH-29 | A12 |
| CH-6 | RES\ | 6 | CH-30 | A13 |
| CH-7 | D0 | 7 | CH-31 | A14 |
| CH-8 | D1 | 8 | CH-32 | A15 |
| CH-9 | D2 | 9 | CH-33 | J3-1 |
| CH-10 | D3 | 10 | CH-34 | J3-2 |
| CH-11 | D4 | 11 | CH-35 | J3-3 |
| CH-12 | D5 | 12 | CH-36 | J3-4 |
| CH-13 | D6 | 21 | CH-37 | J3-5 |
| CH-14 | D7 | 22 | CH-38 | J3-6 |
| CH-15 | A1 | 23 | CH-39 | J3-7 |
| CH-16 | A2 | 24 | CH-40 | J3-8 |
| CH-17 | A3 | 25 | CH-41 | J3-9 |
| CH-18 | A4 | 26 | CH-42 | J3-10 |
| CH-19 | A5 | 27 | CH-43 | J3-11 |
| CH-20 | A6 | 28 | CH-44 | J3-12 |
| CH-21 | A7 | 29 | CH-45 | J3-13 |
| CH-22 | A8 | 30 | CH-46 | J3-14 |
| CH-23 | Phase1 | 32 | CH-47 | J3-15 |
| CH-24 | SYNC | 32 | CH-48 | J3-16 |
J3 header pin assignments
| PIN-1 | PIN-3 | PIN-5 | PIN-7 | PIN-9 | PIN-11 | PIN-13 | PIN-15 |
|---|---|---|---|---|---|---|---|
| CH-33 | CH-35 | CH-37 | CH-39 | CH-41 | CH-43 | CH-45 | CH-47 |
| CH-34 | CH-36 | CH-38 | CH-40 | CH-42 | CH-44 | CH-46 | CH-48 |
| PIN-2 | PIN-4 | PIN-6 | PIN-8 | PIN-10 | PIN-12 | PIN-14 | PIN-16 |
- LogicAnalyzer operation guide: LogicAnalyzer wiki